1. Field of the Invention
The present invention relates to integrated circuits and to integrated circuit non-volatile memory arrays. More particularly, the present invention relates to background auto-refresh techniques for non-volatile memory arrays for programmable logic devices, such as field programmable gate array (FPGA) integrated circuits.
2. Description of Related Art
Non-volatile memories have typical lifetimes in excess of ten years. Therefore there is no need to refresh the memories. This is commonly done in dynamic random access memories (DRAMs) as the memory is stored in capacitors in silicon which slowly leaks, requiring the memory to be refreshed every few milliseconds. Most eNVMs store charge in dielectrics that have leakages that are so low that the charge is retained for many years.
With the current trend towards extreme submicron scaling, the memory cell dielectrics are becoming thin enough that charge leakage is becoming an issue, particularly at high temperatures (125° C.).
It would be advantageous to periodically refresh eNVMs that cannot retain their charge for 10 years at 125° C. to be refreshed periodically. There are two issues with such periodic refresh. One is to determine when to refresh. The second is that refresh is performed under user or system control, thus the initiation is determined by the system such that either no access is attempted during the time the eNVM is being refreshed, or the eNVM can be refreshed in the background, such that the system is never aware that it is being done. This presents some difficulties that need to be addressed. Write times are on the order of milliseconds so, if the memory is to be refreshed in the background, an alternate memory must be used during refresh. In addition, any loss of power during refresh cannot be allowed to cause any loss of data.